- 5 resultados
menor preço: € 17,96, preço mais alto: € 181,99, preço médio: € 50,89
1
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - Kong, Jeong-Taek; Overhauser, David
Encomendar
no/na ZVAB.com
€ 18,24
Envio: € 5,791
Encomendar
Detalhes fornecedor
Link patrocinado
Kong, Jeong-Taek; Overhauser, David:

Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - primeira edição

1995, ISBN: 0792395808

Edição encadernada

[EAN: 9780792395805], Gebraucht, sehr guter Zustand, [SC: 5.79], [PU: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.], White hardcover with white lettering on spine and upper … mais…

NOT NEW BOOK. Custos de envio: EUR 5.79 PsychoBabel & Skoob Books, Didcot, Oxfordshire, OXON, United Kingdom [2917279] [Rating: 5 (von 5)]
fechar(X)
2
Encomendar
no/na ZVAB.com
€ 17,96
Envio: € 5,701
Encomendar
Detalhes fornecedor
Link patrocinado

Kong, Jeong-Taek; Overhauser, David:

Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - primeira edição

1995, ISBN: 0792395808

Edição encadernada

[EAN: 9780792395805], D'occasion, très bon état, [SC: 5.7], [PU: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.], White hardcover with white lettering on spine and upper board… mais…

NOT NEW BOOK. Custos de envio: EUR 5.70 PsychoBabel & Skoob Books, Didcot, Oxfordshire, OXON, United Kingdom [2917279] [Note: 5 (sur 5)]
fechar(X)
3
Encomendar
no/na AbeBooks.de
€ 18,24
Envio: € 5,791
Encomendar
Detalhes fornecedor
Link patrocinado
Kong, Jeong-Taek; Overhauser, David:
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - primeira edição

1995

ISBN: 0792395808

Edição encadernada

[EAN: 9780792395805], Gebraucht, sehr guter Zustand, [PU: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.], White hardcover with white lettering on spine and upper board and co… mais…

NOT NEW BOOK. Custos de envio: EUR 5.79 PsychoBabel & Skoob Books, Didcot, Oxfordshire, OXON, United Kingdom [2917279] [Rating: 5 (von 5)]
fechar(X)
4
Encomendar
no/na Biblio.co.uk
$ 18,01
(aproximadamente € 18,02)
Envio: € 5,891
Encomendar
Detalhes fornecedor
Link patrocinado
Kong, Jeong-Taek; Overhauser, David:
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing) - encadernado, livro de bolso

1995, ISBN: 9780792395805

Norwell, Massachusetts, U.S.A.: Kluwer Academic Publishers, 1995. White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal … mais…

Custos de envio: EUR 5.89 PsychoBabel & Skoob Books
fechar(X)
5
Digital Timing Macromodeling for VLSI Design Verification - Jeong-Taek Kong/ David V. Overhauser
Encomendar
no/na Hugendubel.de
€ 181,99
Envio: € 0,001
Encomendar
Detalhes fornecedor
Link patrocinado
Jeong-Taek Kong/ David V. Overhauser:
Digital Timing Macromodeling for VLSI Design Verification - encadernado, livro de bolso

ISBN: 0792395808

Digital Timing Macromodeling for VLSI Design Verification ab 181.99 € als gebundene Ausgabe: Auflage 1995. Aus dem Bereich: Bücher, Wissenschaft, Technik, Medien > Bücher, Springer US

Nr. 4061883. Custos de envio:, , DE. (EUR 0.00)
fechar(X)
1Como algumas plataformas não transmitem condições de envio e estas podem depender do país de entrega, do preço de compra, do peso e tamanho do artigo, de uma possível adesão à plataforma, de uma entrega directa pela plataforma ou através de um terceiro fornecedor (Marketplace), etc., é possível que os custos de envio indicados pelo eurolivro não correspondam aos da plataforma ofertante.

Dados bibliográficos do melhor livro correspondente

Pormenores referentes ao livro
Digital Timing Macromodeling for VLSI Design Verification
Autor:
Título:
Número ISBN:

9780792395805


Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

Dados detalhados do livro - Digital Timing Macromodeling for VLSI Design Verification


EAN (ISBN-13): 9780792395805
ISBN (ISBN-10): 0792395808
Livro de capa dura
Ano de publicação: 1995
Editor/Editora: Springer-Verlag GmbH
292 Páginas
Peso: 0,602 kg
Língua: eng/Englisch

Livro na base de dados desde 2007-10-21T18:40:29+01:00 (Lisbon)
Página de detalhes modificada pela última vez em 2023-10-27T20:27:12+01:00 (Lisbon)
Número ISBN/EAN: 9780792395805

Número ISBN - Ortografia alternativa:
0-7923-9580-8, 978-0-7923-9580-5
Ortografia alternativa e termos de pesquisa relacionados:
Autor do livro: jeong, kong, overhaus
Título do livro: engineering design, digital timing macromodeling for vlsi design verification, digital design and computer architecture, design and the computer, architecture science

Dados da editora

Autor: Jeong-Taek Kong; David V. Overhauser
Título: The Springer International Series in Engineering and Computer Science; Digital Timing Macromodeling for VLSI Design Verification
Editora: Springer; Springer US
265 Páginas
Ano de publicação: 1995-05-31
New York; NY; US
Língua: Inglês
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
Available
XXI, 265 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Modulation; VLSI; computer-aided design (CAD); design; development; history; integrated circuit; interconnect; model; modeling; simulation; tables; transistor; transmission; verification; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Electrical and Electronic Engineering; Computer-Aided Design (CAD); Elektrotechnik; BC

1 Introduction.- 1.1 Overview of the VLSI Design and Verification Process.- 1.2 Problems in MOS Digital Macromodeling.- 1.3 Contributions of The New Macromodel.- 2 Survey of Simulation and Macromodeling Techniques.- 2.1 Introduction.- 2.2 Circuit Simulation.- 2.3 Macromodeling.- 2.4 Gate-level and Switch-level Simulation.- 2.5 Switch-level Timing Simulation.- 2.6 Fast-timing Simulation.- 2.7 Interconnection Analysis.- 2.8 Mixed-mode/Mixed-domain Simulation.- 3 A Nonlinear Macromodel.- 3.1 Introduction.- 3.2 A Macromodel for the General Case.- 3.3 Macromodeling with Fast Input Transitions.- 3.4 Slow Input and Fast Output Transitions.- 3.5 Experimental Results.- 4 Reduction Techniques for Complex Gates.- 4.1 Introduction.- 4.2 Reduction of Series-connected Transistors.- 4.3 Generalized Reduction Techniques for Complex Gates.- 4.4 Experimental Results.- 5 Accounting for RC-Interconnects.- 5.1 Introduction.- 5.2 Related Work.- 5.3 RC-interconnect Effects.- 5.4 Modeling the Effective Driver-loading.- 5.5 Driver Output Waveform Estimation.- 5.6 Experimental Results.- 6 Transmission Gate Modeling.- 6.1 Introduction.- 6.2 A Gate Driving a Transmission Gate.- 7 Conclusions.- 7.1 Summary.- 7.2 Future Research.- A The Spice Level 2 Model.- B Nonlinear Macromodel Output Response Derivations.- B.1 The Derivation of the Output Response in Region III.- B.2 The Derivation of the Output Response in Region VI.- D Delay Errors for Various AOI Gates.- References.
< Para arquivar...