Memory-Based Logic Synthesis - novo libro

EAN (ISBN-13): 9781441981035
ISBN (ISBN-10): 1441981039
Livro de capa dura
Ano de publicação: 2011
Editor/Editora: SPRINGER VERLAG GMBH
201 Páginas
Peso: 0,454 kg
Língua: eng/Englisch

Livro na base de dados desde 2009-07-10T19:57:24+01:00 (Lisbon)
Página de detalhes modificada pela última vez em 2023-03-01T16:35:48+00:00 (Lisbon)
Número ISBN/EAN: 9781441981035

Número ISBN - Ortografia alternativa:
1-4419-8103-9, 978-1-4419-8103-5
Ortografia alternativa e termos de pesquisa relacionados:
Autor do livro: tsutomu
Título do livro: synthesis, memory

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Dados da editora

Autor: Tsutomu Sasao
Título: Memory-Based Logic Synthesis
Editora: Springer; Springer US
189 Páginas
Ano de publicação: 2011-03-08
New York; NY; US
Impresso / Feito em
Peso: 1,030 kg
Língua: Inglês
106,99 € (DE)
109,99 € (AT)
118,00 CHF (CH)
POD
XII, 189 p.

BB; Energy, general; Hardcover, Softcover / Technik/Wärmetechnik, Energietechnik, Kraftwerktechnik; Umwelt; Verstehen; Embedded Systems; FPGA; Integrated Circuit Design; Logic Synthesis; Memory; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Energy Policy, Economics and Management; Electrical Power Engineering; Mechanical Power Engineering; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Elektrotechnik; Energietechnik, Elektrotechnik und Energiemaschinenbau; Schaltkreise und Komponenten (Bauteile); Computer-Aided Design (CAD); BC; EA

This book describes the synthesis of logic functions using memories. It is useful to design field programmable gate arrays (FPGAs) that contain both small-scale memories, called look-up tables (LUTs), and medium-scale memories, called embedded memories.  This is a valuable reference for both FPGA system designers and CAD tool developers, concerned with logic synthesis for FPGAs.  Anyone using logic gates to design logic circuits, you can benefit from the methods described in this book.  Describes in detail the synthesis of logic functions using memories; Introduces a look-up tables (LUT) cascade as a new architecture for logic synthesis; Shows logic design methods for index generation functions; Introduces C-measure, which specifies the complexity of Boolean functions; Introduces hash-based design methods, which efficiently synthesize index generation functions by pairs of smaller memories and can be applied to IP address tables, packet filtering, terminal access controllers, memory patch circuits, virus scanning circuits, intrusion detection circuits, fault map of memories, code converters and pattern matching.